JOTP-053
11 March 2015
(3) Power up and allow the UUT to perform its functional mission.
(4) Repeat steps 2 through 3 for each adjacent I/O combination.
(5) Allow the UUT to begin its functional mission.
(6) Short two adjacent I/O pins of the complex logic device after applying power. This
shorted condition shall occur before the enabling of any safety features (as shown on the UUT
event timeline within the test plan).
(7) Repeat steps 5 through 6 for each adjacent I/O combination.
(8) Allow the UUT to begin its functional mission.
(9) Short two adjacent I/O pins of the complex logic device after the enabling of the
first safety feature (as shown on the UUT event timeline within the test plan).
(10) Repeat steps 8 through 9 for each adjacent I/O combination.
(11) Repeat steps 1 through 10 for each complex logic device.
(12) Repeat steps 1 through 11 for the remaining UUTs.
b. Test Rationale. The objective of this test is to verify that no safety system failures,
faults, or anomalies occur as of a result of I/O pins on the complex logic devices being shorted at
various points during the mission. This is intended to primarily be proven through analysis with
testing to be conducted on any case that cannot be analyzed.
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