JOTP-053
11 March 2015
analysis shall be conducted for each pin of the complex logic device under test. This analysis shall
address floating pins occurring both, prior to, and after, application of power(s), and at various
stages in the arming cycle. Testing shall be conducted for any case which cannot be determined
via analysis to verify that no safety system failures, faults, or anomalies occur.
5.3.2 Test Procedure - Transient Loss of Ground (Logic Device).
a.
Perform the steps below:
(1) Monitor the test points detailed in the test plan.
(2) Allow the UUT to begin its functional mission.
(3) Apply 3 consecutive cycles of a 50 ms loss of ground condition at 50% duty cycle
to all of the ground pins of the complex logic device. If the program has a specified requirement
for susceptibility to a ground drop-out, that time shall be used in lieu of 50 ms. This drop-out of
ground shall occur before the enabling of any safety features (as shown on the UUT event timeline
within the test plan).
(4) Allow the UUT to begin its functional mission.
(5) Apply 3 consecutive cycles of a 50 ms loss of ground condition at 50% duty cycle
to all of the ground pins of the complex logic device. If the program has a specified requirement
for susceptibility to a ground drop-out, that time shall be used in lieu of 50 ms. This drop-out of
ground shall occur after the enabling of the first safety feature (as shown on the UUT event timeline
within the test plan).
(6) Repeat steps 2 through 5 for each complex logic device.
(7) Repeat steps 1 through 6 for the remaining UUTs.
b. Test Rationale. The objective of the loss of ground test is to determine if any safety
system failures, faults, or anomalies occur as a result of the ground connections being
intermittently removed from the complex logic device prior to arming.
5.3.3 Test Procedure - Shorting of I/O (Logic Device).
a. An analysis with the equivalent rigor of a "bent pin" analysis shall be conducted giving
consideration to the adjacent pins of the complex logic device. This analysis shall address shorts
occurring both prior to, and after application of power, and after the enabling of the first safety
feature. Testing shall be conducted for any case which cannot be determined via analysis.
(1) Monitor the test points detailed in the test plan.
(2) Short two adjacent I/O pins of the complex logic device prior to applying power.
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